On Detailed Routing for a Hierarchical

In modern FPGA CAD ow, netlist routing on a particular routing architecture is solved in two steps, global routing based on wire bandwidth constraints of the architecture, and subsequent detailed routing based on the ner switching constraints of the architecture. Detailed routing is dif-cult and provably NP-complete in popular 2-D mesh architectures such as the Xilinx 4000 series FPGAs 16]. Certain tree based routing architec-tures, which are desirable for scalability and area universality 11], have known polynomial algorithms and guarantees for detailed routing. In this paper we study approaches to detailed routing for a fat-tree routing architecture with restricted switching topology, in which routing bandwidth scales according to Rent's Rule. We discuss several formulations and frameworks for solving the detailed routing problem, using such techniques as graph coloring, multicomodity ow, and integer linear programming.